1. Field of the Invention
The present invention relates generally to the field of frequency synthesizers. Specifically, the present invention relates to the field of digital frequency difference detector, such as used in conjunction variable oscillators to lock onto a reference frequency.
2. Description of the Related Art
Frequency synthesizing operations, such as using a variable oscillator for clock generation, are used in modern communication systems. Such frequency synthesizers are typically analog circuits, but to lower cost it would be desirable to implement such circuits using low cost digital CMOS processes.
A goal of variable oscillators is to synthesize a clock signal whose frequency is a multiple of a supplied reference clock source. It is desirable that the synthesized clock signal be locked onto the reference clock source, i.e. that a pulse edge of the synthesized signal be substantially coincident with a pulse edge of the reference clock source at regular pulse intervals. To accomplish this, precision clock synthesizers traditionally use a phase detector to compare a synthesized clock to a reference source and obtain a measure of their relative phase difference. The measured phase difference is used to adjust the scaled frequency of the synthesized signal, i.e. the generated clock, to match the reference clock frequency.
With reference to FIG. 1, a typical phase locked loop frequency synthesizer generates an Output Clock signal (periodic waveform) at a frequency that is a multiple of a stable Reference Clock Input. In the present case, the generated output clock frequency is a simple integer multiple of the reference clock frequency. It is well known how to extend this prior art frequency synthesizer to provide non integer multiples. The Reference Clock Input signal is traditionally applied to an analog phase and frequency detector (PFD) 201, which includes an analog charge pump. PFD 201 compares the Reference Clock Input signal with a frequency-divided, feedback signal a voltage controlled oscillator (VCO) 205. PFD 201 compares the phase and frequency of the VCO feedback signal with the Reference Clock Input signal to determine if the frequency output of VCO 205 is lower, higher, or locked onto the Reference Clock Input signal, and output a control signal, accordingly. The output from PFD 201 is passed through a low pass, loop filter 203 and applied to a control input of VCO 205, which adjusts the frequency of its synthesized Output Clock signal accordingly. At this point a synthesized Output Clock signal, or a proportional signal, is fed back through frequency divider 207 to repeat the process.
As shown, prior art designs generate the control voltage for the voltage controlled oscillator using a phase detector, or a combination phase and frequency detector, and a charge pump. Both of these approaches require a low pass loop filter to lock the VCO to the reference clock input. For high accuracy and low jitter synthesizers, the loop filter must have a low bandwidth which implies that the filter components are large. Note that the conventional prior art phase and frequency detector generates an output voltage which is strongly dependent on phase difference and weakly dependent on frequency difference. The loop filter must be designed to filter both responses. The near in phase detector response typically determines the filter characteristics to insure loop stability, which implies that the frequency dependent component is filtered very strongly. Furthermore, this use of phase to adjust frequency introduces instability into the frequency synthesis loop for well known reasons.
The use of a frequency difference detector to directly measure the frequency difference between the reference signal and the synthesized signal would be preferable to adjust the synthesized frequency. However, stable and easily implemented frequency only difference detectors are not known in the art. Combined phase/frequency detectors are well known, as shown in FIG. 1.
Prior art frequency only detectors have traditionally been complicated circuits involving the generation of analog signals at beat frequencies (which are the sum and difference frequencies of the reference and scaled synthesized clocks) and filtering the resultant signals to generate the required correction voltage for the synthesized, i.e. generated, clock oscillator. The use of analog signals is inconvenient since the clocks and scaling circuits of modern clock synthesizers are based on digital circuitry. A digital frequency difference detector is therefore desirable.